The present invention relates to a complementary-metal-oxide-semiconductor (CMOS), and more specifically, to dual isolation on a strained silicon-on-insulator (SSOI) wafer.
A fin field effect transistor (finFET) is a type of metal-oxide-semiconductor FET (MOSFET) in which a conducting channel is wrapped by a silicon fin. A finFET device may be a complementary metal-oxide-semiconductor (CMOS) device that includes a p-type metal-oxide-semiconductor (pMOS) finFET device or pFET and an n-type metal-oxide-semiconductor (NMOS) finFET device or nFET formed on a substrate. A silicon-on-insulator (SOI) wafer includes a substrate with a silicon layer having a neutral silicon lattice. When the silicon lattice is bigger than a neutral silicon lattice, the silicon is said to be under tensile strain. This is typically the strain experienced in an SSOI wafer. When the silicon lattice is smaller than a neutral silicon lattice, the silicon is said to be under compressive strain. As noted, a finFET (e.g., CMOS device) may include an n-channel region (nFET) and a p-channel region (pFET) with silicon (Si) and silicon germanium (SiGe) fins, respectively. While an SSOI substrate may improve performance in the nFET, the tensile strained SSOI substrate may cause mobility degradation in the pFET channel region.